Axilog is a set of language annotations for approximate hardware design and reuse in Verilog. Axilog enables the designer to relax the accuracy requirements in certain parts of the design, while keeping the critical parts strictly precise. Axilog aims to facilitate the approximate hardware design by providing:

• Necessary synatx and semantics for approximate hardware design.
• Automatic analysis to infer the relaxable gates and connections from the designer's annotations.
• An abstraction layer between the hardware designer and the details of the approximate synthesis flow.