Design Builder contains a generic template for stochastic gradient descent, which is used across all range of statistical machine learning algorithms. These accelerator templates are pre-designed by expert hardware designers and resued for learning algorithms that use stochastic gradient descent. Moreover, the template provides the intefacing logic between accelerators and the rest of the system.

**Source: D. Mahajan, J. Park, E. Amaro, H. Sharma, A. Yazdanbaksh, J. Kim, H. Esmaeilzadeh. TABLA: A Unified Template-based Framework for Accelerating Statistical Machine Learning. In HPCA, 2016**

As shown in the figure, all the learning algorithms above have one thing in common: stochastic gradient descent. Given the programmer's implementation of the gradient function, the design builder generates the corresponding synthesizable Verilog code.

The figure above is a clustered template architecture that is scalable, general, and highly customizable. The design builder shrinks or expands this template design considering the degree of parallelism in the Data Flow Graph and the availability of the resources in the target FPGA. The design builder first extracts the maximum number of parallel operations from the Data Flow Graph and select the total number of the Processing Engines accordingly.